Synopsys has added AI-based Verification and Test to its already-successful Design solution, DSO.ai, with more to come.

Three years ago, Electronic Design Automation (EDA) solution provider Synopsys took the bold step to add reinforcement learning to its chip design software and has since enabled its clients to design and tape-out over 100 new chips with superior power, performance, and area and get these chips to market faster than traditional design techniques. AI in chip design has become a huge deal; we expect Synopsys will help 1000 customers build more optimized chips with fewer resources by the end of the year; a massive assist in an industry short of resources.

During the annual SNUG user group meeting, Synopsys CEO Aart de Geus announced “Synopsys.ai”, once again lapping his competitors. Synopsys.ai is an umbrella portfolio wherein nearly the entire EDA workflow is being augmented with AI, generally using reinforcement learning and available on site and in the Microsoft Azure cloud.

What is Synopsys.ai?

Synopsys.ai is a portfolio of EDA development tools that have all been enhanced with Artificial Intelligence. Over time, Synopsis will add AI to virtually the entire suite of tools to help engineering teams design better chips, and do so with fewer engineers. The USA Chips Act is great, but we just don’t have adequate engineering to effectively re-establish the USA as a leader in chip design and manufacturing without using AI. By some estimates, the United States needs at least 50,000 new semiconductor engineers over the next five years to staff all of the new factories and research labs that companies have said they plan to build with subsidies from the Chips and Science Act.

Synopsys.ai includes:

  • Digital design space optimization to achieve power, performance and area (PPA) targets, and boost productivity (used in 100 production tape-outs by January 2023). (DSO.ai)
  • Analog design automation for rapid migration of analog designs across process nodes.
  • Verification coverage closure and regression analysis for faster functional testing closure, higher coverage and predictive bug detection.
  • Automated test generation resulting in fewer, optimized test patterns for silicon defect coverage and faster time to results.
  • Manufacturing solutions to accelerate development of lithography models with high accuracy to achieve the highest yield.

One of the time-consuming steps in chip design is the development of wide testing coverage in design verification. Here, AI can be used to generate test cases automatically based on predefined test coverage goals and constraints. Historical data can be used to generate new test cases that increase coverage and detect potential errors. This can reduce the need for manual test case generation and increase the efficiency and effectiveness of the verification process.

In the area of automated testing, AI has been added to detect faults and errors in chip designs more accurately and efficiently than traditional techniques. Machine learning algorithms can be trained on historical data to identify patterns and indicators of potential faults in chip designs. This can enable chip designers to detect and diagnose faults more quickly and accurately, reducing the risk of errors and delays in the verification process. Spending less time on a tester means getting a chip to market faster.

TSMC, IBM, MediaTek and Renesas have publicly stated support for Synopsys’ AI-driven EDA design strategy with significant benefits already being realized. Renesas achieved a 10x productivity gain using AI-driven verification for deep bug hunting, resulting in higher coverage. MediaTek observed significant test pattern reduction improving overall test time.

“As the industry moves from Nanometers to Angstroms, chip complexity is going to skyrocket,” said Thomas Anderson, Vice President, AI and Machine Learning at Synopsys. “Consequently, AI is becoming an absolute necessity for chip design teams to embrace and adopt.”

Conclusions

As we predicted when we first wrote about Synopsys DSO.ai, we are just seeing the tip of the iceberg when it comes to applying AI to the chip design workflow. Dr. de Geus has now fleshed out his vision of using AI to help speed the entire process, solutions which should help alleviate the shortage of highly trained engineers needed to realize the goals of the USA Chips Act, and help design teams around the world.

Silicon is at the heart of practically every innovation in today’s digital world. Being able to accelerate the design, verification, testing, and manufacturing of state-of-the-art semiconductors with fewer engineers will be a boon to the companies that embrace AI. And a competitive threat to those that do not.

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